1. Field of the Invention
The present invention relates to setting the states of multiple sequential processing units into mutually compatible states without resorting to a common reset signal.
2. Discussion of the Background
In order to synchronously operate a plurality of sequential electronic circuits arranged e.g. within an electronic system, all involved circuits must be set into mutually compatible states at some point in time. Provided that all involved circuits update their state under control of a clock signal derived from a common reference clock, their states will remain synchronous ever after.
The need to synchronize the states of multiple circuits arises in particular in communication systems comprising e.g. a transmitter scrambling a data stream by combining the data with a pseudo-random bit stream (PRBS) through an exclusive- or operator e.g. for privacy or other purposes. In order to retrieve the original data, the receiver must generate the same PRBS and combine it with the received scrambled data. If the states of the transmitter PRBS generator and the receiver PRBS generator are not properly synchronized then the descrambler output does not match the original data and reception errors occur.
In the prior art, a number of devices are known which superficially resemble the invention in that they also introduce phase shifting elements in the clock paths of a plurality of sequential processing units for synchronization purposes. The fundamental difference with respect to the invention is that these devices seek to synchronize the times at which the processing units update their states whereas the invention seeks to synchronize the states themselves. Considering the example where the processing units consist of two digital counters, the prior art reviewed below seeks to achieve that both counters increment their count value at exactly the same time (never mind whether the count values are identical or not). By contrast, the invention seeks to ensure that the count values are identical in both counters (never mind whether they update their states at exactly the same time or not) as an alternative to the distribution of a common reset signal for high frequency applications where the reset signal approach is not practical.
In an internal clock signal generation circuit as disclosed in U.S. Pat. No. 5,663,668 B1 a plurality of internal clock signals of different phases are generated based on an external clock signal. The internal clock signals are synchronized with the external clock signal by a PLL circuit. The plurality of internal clock signals are respectively supplied to a plurality of internal circuit blocks. Since the phases of the generated internal clock signals are different the phases of the internal clock signals arriving at the internal circuit blocks can be matched even if delays of the signals between the internal clock signal generation circuit and the plurality of internal circuit blocks are different.
A multiple-phase clock signal generator as disclosed in U.S. Pat. No. 5,517,147 B1 includes a phase-locked loop (PLL) for generating an oscillating signal having a predetermined frequency, a counter driven by the oscillating signal and having a plurality of outputs, and a plurality of combinational logic gates each having a plurality of inputs and an output. Selected ones of the inputs of each combinational logic gate are coupled to selected outputs of the counter to produce, at the output of each combinational logic gate, a clock signal having a particular phase. Different combinations of the outputs of the counter can be used to generate different phases.
In order to enable the adjustment of clock tree delays independently from each other, an apparatus is disclosed in EP 1 385 267 A1 for generating at least one phase-shifted version of a reference clock signal within an integrated circuit having a plurality of blocks which require to be supplied with phase-shifted versions of said reference clock signal. This apparatus comprises a single phase-locked loop receiving the reference clock signal at an input thereof and for generating an adjusted clock signal at an output reference point and a clock tree connected to the output reference point of the phase-locked loop for distributing the adjusted clock signal to a first one of the plurality of blocks. An output node of the clock-tree is connected to a feedback input of the phase-locked loop. At least one additional clock tree connected via at least one delay element to the output reference point of the phase-locked loop for distributing a phase-shifted clock signal to additional ones of the plurality of blocks.
The state synchrony is also required for digital data communications over a single high-speed serial line through serializer/deserializer circuits (SERDES) as depicted in FIG. 5. A transmitter serializes the data incoming as parallel B-bit wide words onto a single high-speed serial bit stream under control of a clock signal. The receiver must sample the bit stream at exactly the same rate as the transmitter clock and at an appropriate phase in order to minimize the probability of transmission errors. Moreover, the states of the deserializer and serializer must also be synchronized in order to recover the original word boundaries. In this case, a synchronization offset between the serializer and deserializer states must be known. If the deserializer begins to operate at a random point in the bit stream then the output words may be shifted with respect to the original words which results in reception errors.
The state synchrony may further be required for circuits arranged within measurement instruments such as digitizing oscilloscopes measuring multiple waveforms simultaneously in the time domain. In order to e.g. display multiple waveforms with correct timing relationships, it is necessary to preserve information about the time at which the samples were acquired by each channel in order to guard against possible latency differences across channels in the subsequent signal clock signal paths.
For synchronization purposes, a synchronization pattern generator may be incorporated within an analog/digital converter (ADC) of each channel as shown in FIG. 6. The synchronization pattern generator may comprise a periodic pulse generator with a period exceeding the largest expected timing mismatch between the channels. Alternatively, the generator may comprise a counter incrementing a value at every sample time instant. The state of the counter may be output with every sample or at specific times, e.g. with the beginning of an acquisition of a new record. For example, at least once per waveform acquisition, the state of the counter can be recorded into memory along with the digitized sample amplitudes in order to preserve timing information for subsequent time-alignment across channels.
For a proper operation, all channels preferably should sample the input signals at the same frequency and phase relationship. Moreover, the internal states of the synchronization pattern generators should match across the channels so that a timing pattern represents the same time basis for all channels.
In order to operate a plurality of circuits at the same frequency, a common clock signal may be distributed to all circuits as depicted in FIGS. 5 and 6.
At low clock frequencies, the states of a plurality of circuits may further be synchronized by distributing a common reset signal forcing all circuits into a known initial state. After the reset signal is released, the states remain in synchrony provided that the circuits operate on a common clock signal. However, if the distance between circuits is non-negligible compared to the clock wavelength then timing errors exceeding a clock period may occur due to mismatches between the lengths of electrical paths, between the driver characteristics and between the termination impedances.
With reference to FIG. 6 for low-frequency applications, the counters in all ADC chips can be reset to zero at power-up. Thereafter, all counters will hold the same value because they run on the same clock signal. Subsequent to waveform acquisition, data samples measured simultaneously in different channels can be identified in that they are associated to the same counter value.
As an alternative to a common reset signal, it would be possible to let the counters in all ADC chips start from a random initial state. In a first step, it would be necessary to measure the difference between counter states at one point in time. For example, this step could be performed by measuring the same reference signal through both channels of the instrument and comparing the measurement data across channels. Once matching data samples have been identified, the difference between a recorded counter value associated with these samples indicates the amount of offset between the counters. This difference can be cancelled in all subsequent measurements by adding it to the time tags issued by the channel with the lowest counter values. Thus, there is no attempt to modify the states of the counters while they run. Only the recorded data is corrected.
Another approach consists of starting the counters from random initial states and measuring the difference between counters. However, the corrective step consists of incrementally modifying the states of the counters while they run until the two counters reach the same state. Such modification of states may consist of speeding up or slowing down one of the counters temporarily. For instance, the counters may be designed in such a way that they increment by one unit per clock cycle in normal operation, but can optionally increment by zero (in order to slow down) or by two units (in order to speed up) on some clock cycles as a mean to reduce the offset between counters across chips.
A possible approach to ensure synchrony may comprise distributing a common reset signal and asserting it at one point in time in order to reach a known initial state and distributing a common clock signal and making all circuits update their state on transitions of this clock signal.
Another solution for shifting the state of a circuit consists of skipping clock cycles. Upon detection of a state offset, a circuit may let one or more clock cycles go by without updating its own state while other circuits running on the same clock signal keep operating normally. As a result, when this circuit resumes normal operation, its state has been delayed with respect to the states of the other circuits. In principle, clock cycle skipping could be implemented by inserting a cycle skipping circuit in the clock path of an existing circuit and does not necessarily require modifying the internal design of the circuit to be synchronized.
Instead of slowing down the circuit, it would also be possible to speed it up by skipping states compared to the state sequence in normal operation, where a counter increments by two units instead of one. However, this approach requires that the state skipping feature be built into the circuit from the start.
At very high clock frequencies, it may not be practical to distribute a common reset signal to multiple circuits to be synchronized. If the distance between circuits is greater than the wavelength of the clock signal, it may become challenging to achieve good delay matching between the clock signal path and the reset signal path, whereby proper timing relationships between the clock and the reset signals become difficult to guarantee. For this reason, it may be necessary to resort to other means for setting multiple circuits running on the same clock signal into mutually compatible states.
In cases where a distribution of a common reset signal is not feasible, an alternative approach comprises letting all circuits start in random initial states, measuring the offsets between states at one point in time, and correcting the impact of state offsets at all times thereafter.
This approach is suitable for applications where the impact of state offsets, once known, can be corrected. No attempt is made to modify the circuit states themselves while they run. The random initial state offsets remain constant because all circuits run on the same clock signal.
Another possible approach to circumvent the need of a common reset signal consists of:
1. letting all circuits start in random initial states;
2. measuring the offsets between states at one point in time; and
3. modifying the states in some circuits during operation in such a way to obtain mutually compatible states.
Iterations between steps 2 and 3 may be necessary until all circuits have reached mutually compatible states.
A further synchronizing approach is based on transmitting a data stream encoding the state of a circuit with respect to another circuit. This approach is particularly suitable in data communication systems where a data link exists between two circuits to be synchronized. This approach is suitable for synchronizing in the aforementioned scrambler/descrambler-systems where the descrambler automatically recovers the state of the scrambler from the received data bits. However, such a self-synchronizing scheme is suited only for this specific application. It also has the drawback that the scrambler can remain locked in an unwanted state for some incoming data sequences. Thus, scramblers with a large number of state bits must be used in order to reduce the probability of failure which increases the hardware complexity and power consumption.
In order to deal with synchrony errors in high-speed circuits, random initial states may be accepted which requires a posteriori correcting the effect of state misalignment. Referring to the aforementioned SERDES embodiment, a subset of B bits may e.g. be used for transmitting a synchronization pattern marking a word boundary. The receiver deserializes the incoming bit stream starting at a random point and subsequently searches for the synchronization pattern at all possible locations in the B-bit wide parallel output word. A word alignment may be realized by shifting the parallel output words using e.g. a digital barrel shifter. However, the number of logic gates required to implement a B-bit barrel shifter grows with the square of B which is associated with an increasing in hardware complexity and power consumption.
The aforementioned multi-channel measurement instrument demonstrates another case where the effect of random initial states can be corrected a posteriori instead of a priori controlling the states of the circuits. In an initial calibration step performed after a power-up, a suitable common reference signal (e.g. a sine wave or a square wave) can be measured through all channels, wherein the delays between the measurement channels can be calculated from the sample data streams assuming the same original signal. The offsets between the timing patterns across the channels are also calculated. From this information, the relationship between the timing pattern generated by each channel and a common time scale can be determined. As long as the instrument remains powered up, this relationship will remain unchanged. The timing patterns recorded in subsequent measurements can be corrected on this basis which is, however, associated with an increased complexity.